1. Field of the Invention
This invention relates to logic gate circuitry in general and, more particularly, to emitter-coupled logic output buffer circuitry.
2. Description of the Prior Art
Most integrated circuit packages have limitations on the amount of power a chip (or chips) within the package may dissipate. Exceeding that limitation will cause thermal runaway in the chip, potentially resulting in the catastrophic failure thereof. However, it is generally desirable to place as many gates as possible in each package for increased functionality of the system or subsystem the package is placed in.
In large scale digital integrated circuits having thousands, or even tens of thousands, of logic gates, the power dissipated by each gate is reduced as much as practically possible so as not to exceed the maximum power rating of the package. However, it is recognized that not all the gates drive the same loads; some gates drive other gates on the same chip while others need to drive off-chip gates or terminated low-impedance transmission lines and buses. Hence, it typically the case that while the gates are optimized for minimum power dissipation at a predetermined speed, buffers are provided where a gate needs to drive other gates that are off chip. These buffers are of much higher power than the gates driving them but there are relatively few buffers on each chip. This is illustrated by a simplified diagram shown in FIG. 1. Here a first chip 2 in a system 1 communicates via a bus 3 (typically terminated with 50 .OMEGA. terminations) to a receiver 4 on a second chip 5. Driving the bus 3 on chip 2 is a buffer 6 which is driven by gate circuitry 7. There may also be other chips 2,5 on the same bus 3. Similarly, chip 2 may have other buffers 6 driving other buses 3. Because bus 3 may load (usually capacitively) the output of the buffer 6 more than the loading of the buffer 6 on the output of the gate 7, the power handling capacity of buffer 6 will be greater than the power handing capacity of gate 7. The increase in power handling capacity is usually achieved at the expense of higher power dissipation by the buffer 6.
Since a buffer typically does not perform a "logical" function, such as an AND or OR function, the propagation delay of a buffer is an overhead which slows down the overall speed of the logic on the chip. Therefore, it would be desirable to have a buffer circuit which has a small propagation delay without dissipating a lot of power. Alternatively viewed, the bandwidth of the buffer must be wide enough to accommodate the desired speed of the system 1.
For raw speed, emitter-coupled logic (ECL) is the popular choice for the logic type or family in high-speed digital systems. The price paid for such speed is high power dissipation, as discussed above. An ECL family designed for very highspeed applications is the 100K series, made by many manufacturers, such as the Fairchild Company, of Santa Clara, Calif. A typical buffer 10 in the 100K family is shown in FIG. 4. Inputs IN+,IN- couple to transistors 11, 12, forming a differential pair. The common emitters of the differential pair, referred to here as a tail, couple to a current source 13. The collector outputs of the differential pair (transistors 11, 12) couple to load resistors 14, 15 which in turn couple to a power source, here ground. The outputs of the differential pair also couple to a pair of emitter followers 16, 17, the emitters of which couple to the output of the buffer, OUT+,OUT-. A clamping circuit of resistor 18 and paralleled diodes 19, 20 serves to limit the voltage swing of the outputs of the differential pair (11, 12) and provide thermal compensation of the logical "high" and "low" output voltages. The combination of the current from current source 13, the resistances of the loads 14, 15, the clamping voltage of resistor 18 and diodes 19,20, and the base-emitter voltages of transistors 16, 17 determine the logical "high" and logical "low" output voltages on OUT+,OUT-. The clamp circuit (18,19,20) adds considerable amount of capacitive loading between the collectors of transistors 11, 12 and from the collectors to ground. This considerably slows down the operation of the buffer 10 compared operating the buffer without the clamp. Further, the design of the buffer is a compromise between speed, output voltage variations with temperature, and power dissipation. The component values of this design cannot be easily adjusted to optimize the buffer's performance in any or all of these factors.